1. Field of the Invention
The present invention relates to an optical lithographic technology for forming microstructured patterns, more particularly to a method for exposing a light thereby to manufacture semiconductor devices.
2. Description of Related Art
In order to integrate semiconductor memories and microprocessors and speed up their operations more significantly, it will be unavoidable that the structure of the ULSI used for each of those devices must be formed precisely more and more. The most important item for such microstructure of an ULSI is microstructuring of the optical lithography. At present, the lithography technique can form patterns in a size just under the light wavelength of the object lithography apparatus. For example, in the case of a 1 GB DRAM, a lithography apparatus that uses a light source of KrF excimer laser whose wavelength is 0.248 xcexcm must form word and data lines at a width of 0.16 xcexcm respectively.
In order to form a pattern in a size under the wavelength such way, super-resolution techniques such as phase shifting, off-axis illumination, etc. are used. The super-resolution technique is effective for forming line and space (LandS) patterns in which simple lines such as word and data lines are formed in a memory repetitively. This is because the phase of a light passing adjacent line patterns is shifted by 180xc2x0, thereby the diffracted lights kill each other at each boundary between line patterns and a space pattern is formed there respectively. In the case of such super-resolution technique, the coherent factor is set to about 0.3, which is smaller than usual, thereby to increase mutual light interferences.
LandS patterns can be formed in a size under the wavelength using the above method. However, it is found that the method is confronted with problems when forming a pattern off the lines and spaces (LandS), for example, when forming connecting portions between a memory array and a peripheral circuit. This is because the light is diffracted at ends and corners of interconnects and the diffracted lights interfere each other, thereby a resist pattern becomes thinner than the master pattern there. And in the worst case, break failures occur in those interconnects. Hereunder, description will be made for new facts found by the present inventor, etc. through investigation with respect to the above problems.
FIG. 14 shows an explanatory view of such a new discovery. FIG. 14(a) shows a conventional masking pattern for the word lines (WL) at a boundary between a memory array and a sub-word driver (SWD) or a word shunting area of a DRAM. In the sub-word driver (SWD), each word line is expanded to form a dog bone pattern so as to secure a space for placing a contact thereon. In this example, a sub-word driver (SWD) and a memory array are disposed alternately as to be described later in detail. The word lines WLO, 3, 4, and 7 are connected to the left side sub-word driver (SWD) and the word lines WL1, 2, 5, and 6 are connected to the right side sub-word driver (SWD).
FIG. 14(b) shows a concept chart of a resist pattern obtained through a lithographic treatment performed for the pattern shown in FIG. 14(a) using a lithography apparatus on the following conditions of the light source; KrF excimer laser of a wavelength of xcex=0.248 xcexcm, numerical aperture of the lens NA=0.6, coherent factor "sgr"=0.3, and reduction rate K=⅕. And, short failures have occurred between the ends of adjacent word lines (WL) and break failures have occurred around dog-bone portions. Those failures are caused by bad influences of light interferences.
Hereunder, this phenomenon will be described concretely through an optical simulation. In this simulation, contour lines of the light intensities obtained on a resist film are computed on the basis of the master pattern and the optical constants of the lithography apparatus. FIG. 15(a) shows a conventional masking pattern for the tips of word lines. The width and space of each word line are set to 0.16 xcexcm. The optical constants are xcex=0.248 xcexcm, NA=0.6, "sgr"=0.3, defocusing=xe2x88x920.5 xcexcm, and a spherical aberration is assumed. A phase-shift lithographic technique is used in this simulation. A 0xc2x0-phase is assigned to each pattern shown with right-up oblique lines and a 180xc2x0-phase is assigned to each pattern shown with right-down oblique lines. Principally, similar results can also be obtained with the off-axis illumination lithography technique. In all the subsequent simulations, the same optical conditions are assumed. A reduction projector is used for exposure in the optical lithography. In the case of light exposure at a reduction rate of K(K less than 1), the actual circuit pattern and the resist pattern are expanded by K times the masking pattern respectively. For example, at K=⅕, the line width of the masking pattern is 0.8 xcexcm so as to obtain an interconnect width of 0.16 xcexcm, but the masking pattern is reduced to the same size as those of the circuit pattern and the resist pattern for simplification thereafter. FIG. 14(b) shows the distribution of light intensities, obtained as an optical image through computation from this pattern. In other words, FIG. 14(b) shows the contour lines of the relative light intensities of 0.18, 0.32, and 0.53 respectively. The light intensity is defined as 1 for the light transmittance in an enough large pattern. The same three contour lines are indicated in all the subsequent optical simulation results.
FIG. 15(b) shows a resist pattern that can obtain a contour line actually from a light intensity of 0.32. Word lines are formed at equal pitches at places away enough from the ends of the resist pattern. However, the contour line for a light intensity of 0.18 (the outermost line in the pattern) is not separated from adjacent word lines at the tips of the lines. This indicates that the light intensity is not lowered enough at this portion due to the effect of the light interference. Consequently, the resist remains after the development, thereby causing short failures to occur between word lines at a rather high possibility.
In such a dog-bone portion, the contour line of the light intensity of 0.53 breaks. This is because the light intensity in that portion is low. Consequently, the resist will be thinned and there is a high probability that break failures will occur there in the development process.
FIG. 16(a) shows a conventional masking pattern for the tips of the second word lines. In this example, the sub-word driver (SWD) or shunting area is disposed at the left side of each corresponding memory array and all the word lines are connected to their left side sub-word driver (SWD) . Even in this case, the contour line of the 0.18 light intensity (the outermost contour line in the pattern) is not separated from adjacent word lines, so there is a high probability that short failures will occur between those word lines.
Under such circumstances, it is an object of the present invention to prevent short and break failures from occurrence at the tip of each LandS pattern, etc.
In order to achieve the above object, the semiconductor of the present invention, when many word and data lines are laid out at equal pitches in an object memory, allows tips of adjacent lines to be terminated differently in length in the lengthwise direction. With such a disposition of adjacent lines, it is possible to weaken the effect of diffracted light interferences to occur at the tip of each line when in wiring of a pattern, thereby preventing short and break failures.
Such wiring is possible with exposure using a masking pattern in which adjacent patterns are terminated differently in length in the lengthwise direction. For example, in the masking patterns shown in FIG. 11(a), the tips of the adjacent patterns are shifted from each other in the lengthwise direction. If these masking patterns are used for exposure, the distribution of light intensities will become as shown in FIG. 11(b). It would be understood from FIG. 11(b) that there is little possibility that break and short failures occur, since they are separated properly in the pattern.
The difference of length between adjacent wirings at their tips should be over xc2xd of the wiring pitch. With this difference of length, short and break failures can be prevented more effectively. In addition, the difference of length between those adjacent wirings at their tips should be under the wiring pitch. With this difference of length, the redundant chip area can be minimized.
If the present invention applies to the word and data lines of DRAM, SRAM, flash memories, and mask ROM, it will be able to effectively prevent short and break failures in manufacturing processes.
Furthermore, according to the present invention, an exposure process is performed using masking line patterns provided with a side that is not in parallel to the short and long sides of each of those patterns respectively. The masking patterns are formed so that a corner of each line pattern is cut and the pattern is tapered toward the terminal portion. Consequently, the effect of diffracted light interferences can further be reduced. For example, in the case of the masking patterns shown in FIG. 10(a), the adjacent line patterns are terminated differently in length so as to be shifted from each other at their tips in the lengthwise direction and a corner of each line pattern is cut. If such masking patterns are used for an exposure process, the distribution of light intensities becomes as shown in FIG. 10(b), preventing break and short failures. It is thus possible to significantly reduce the possibility that break and short failures occur by using such corner-cut masking patterns. Although FIG. 10 shows masking patterns that are terminated differently in length so as to be shifted from each other at their tips in the lengthwise direction, the effect of diffracted light interferences can also be reduced to a certain extent, and accordingly short and break failures can be reduced even when the patterns are terminated at the same length if a corner of each line pattern is cut such way.
If the exposure light wavelength of the lithography apparatus is assumed to be xcex and the numerical aperture is to be NA, especially when the wiring pitch is less than xcex/(NA), then short and break failures will occur at tips of wirings. The above masking patterns will thus be effective to eliminate such failures.
The present invention can prevent such short and break failures if it applies to (1) word line patterns at a boundary between a memory array and a word-line driver, (2) word-line patterns at a boundary between a memory array and a word-line shunting area, and (3) data line patterns at a boundary between a memory array and a sense amplifier. In addition, the present invention can also apply effectively to the tip of the gate of each MOS transistor in a gate array.
Using the asymmetrical word lines of the present invention will thus be able to reduce the possibility that short failures will occur between those adjacent word lines at the boundary between a sub-word driver and a memory array, as well as between a shunting area of the word lines and a memory array. In addition, it will also reduce the possibility that break failures will occur at dog-bone patterns with which those word lines comes in contact when word lines are formed more precisely at a line width under the size of the light wavelength of the object lithography apparatus using an optical lithographic technique.
In the same way, using the asymmetrical data lines of the present invention will be able to reduce the possibility that short failures will occur between those adjacent data lines at the boundary between a sense amplifier and a memory array, as well as the possibility that break failures will occur at dog-bone-patterns with which those data lines comes in contact when data lines are formed more-precisely at a line width under the size of the light wavelength of the object lithography apparatus using an optical lithographic technique.